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ǰλ к˃xO޹˾ > > yx > ׿Ӱ
ëƬqvod,³һ³ɫ,׿Ӱ

(1)

ϵy飺

ԓϵyɶyͨM(ͨͨͨͨʮͨ)yͨͬr䓹ëƬqvod,³һ³ɫ,׿ӰбںMھy䓹ܱںֵСֵԼƽֵֵ͔ʽڽK˷ܛM@ʾͨͨԼʮͨЌ䓹ƫMЙzyĹܡ䓹ܵ⏽yɃɂy^Mɣrھzy䓹⏽䓹⏽ĜyYһa䓹ƫxyɵ䓹ܱںy`ԱC䓹ܵĜyȡ䓹⏽ֵСֵƽֵֵ͔ʽڽK˷ܛM@ʾ߀Ը͑ľw䓹ܵĜضȜy䓹ܵLȜyܣyȫRڽK˷ܛУyYȫϵyĴУԱCÿһ䓹ܵĔMӛ䛱档

(2)

һ 䓹ƫĜy(ͨ)

ψDʾƽں񔵓LsLk1Lk5Ӌƽõʽ£

LS = [Lk1 + Lk2 + Lk3 + Lk4 + Lk5] / 5

ƽںʣͨ^һǶȵ傀ͨĔľC̎(?S׃)Եõ_ҽY䓹ܱںD

(3)

y񲿷

æ侀͸ʽyʽÿͨķԴxҲãеİbʽ侀͸ܲģв侀գδյIJ䵽xңʹеĚwx,aԓ΢ŴŴ늉̖ٽxD׃0-20ma̖hؙC̖A/DDQٽwһ̎ǾУضa|aӋ㣬Kóֵ

(һ) Ҫc?

񡡾cԄУܡÿܲͨ^ĕrggȣԄMcУԴ˥׃Դ̽yĴǰsëƬqvod,³һ³ɫ,׿ӰصӰ푡?

̽^cC֮gøx̖ݔɔ_ݔxh

()yϵyg

(4)

׿Ӱ

y

1.0-30mm

ٶȷ

<10m/s

ɘӕrg

6ms

ӑB

0.5%0.05mm (2)

oB

0.1%0.01mm (2)

a

10%

ضa

750-1300

ƫa

80mmϞ25mm80mmž15mm

ʽ

BmھrԄӜy

y^cCx

<1.2Km

ͨӍ

x̫WλCҪͨӍfh

ݔ̖

̖⏽̖ض̖L̖ ƫ̖

y

Ãɂ߾CCDR^ͬһƽ90ȽDzֱ܈ƷIJ÷ʽyγwҕǣ@䓹λ׃ëƬqvod,³һ³ɫ,׿ӰлĎ׺`ͬryxɌyƫxyģıںy`MƽʾDD2

(һ) Ҫc?

񡡜yϵyYOӋΣFֻДz^ͱԴ䣬^һ̖|(ԴRS-422̖ͨ)cվCϵy“ϵb{ԇݡ?

񡡜y̽yøFPGA̎˾вɘٶȿ졢yrԺõЧ?

񡡜y̽y߂䌍rԄ{عrgĹܣaھʹÕrԜpСF҉mFӰ푡

(5)

() yϵyg

pCCDyx

Wԭ⣩

7450ؾCCD4um

׿Ӱ

FPGA

y

51-200mm

ٶȷ

<10m/s

ɘӕrg

0.5ms

ֱ

0.05mm/pixel()

ӑB

0.1mm (2)

ضa

286-1300

³һ³ɫ

BmھrԄӜy

ͨӍʽ

RS-422

y^cCx

<4Kmɹwݔ

(6)

ġyؼyL

(һ) ϵyg

ty؃x

ty

y

500-1400

y

1.0%

L

ʽ

BmھrԄӜy

̖ݔʽ

4-20mA

y^cCx

<1Km

(7)

() yLϵyg

yLx

ëƬqvod

Ч

y

y ٶȣ

0-80m/s

y

1.0

750-1300

׿Ӱ

BmھrԄӜy


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ICP14002828̖
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